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ISL59440
Data Sheet October 10, 2007 FN6162.2
400MHz Multiplexing Amplifier
The ISL59440 is a 400MHz bandwidth 4:1 multiplexing amplifier designed primarily for video switching. This Muxamp has user-settable gain and also features a high speed three-state function to enable the output of multiple devices to be wired together. All logic inputs have pull-downs to ground and may be left floating. The ENABLE pin, when pulled high, sets the ISL59440 to the low current power-down mode for power sensitive applications - consuming just 5mW.
TABLE 1. CHANNEL SELECT LOGIC TABLE S1 0 0 1 1 X X S0 0 1 0 1 X X ENABLE 0 0 0 0 1 0 HIZ 0 0 0 0 X 1 OUTPUT IN0 IN1 IN2 IN3 Power Down High Z
Features
* 411MHz (-3dB) Bandwidth (AV = 1, VOUT = 100mVP-P) * 200MHz (-3dB) Bandwidth (AV = 2, VOUT = 2VP-P) * Slew Rate (AV = 1, RL = 500, VOUT = 4V) . . . . .1053V/s * Slew Rate (AV = 2, RL = 500, VOUT = 5V) . . . . .1470V/s * Adjustable Gain * High Speed Three-state Output (HIZ) * Low Current Power-down. . . . . . . . . . . . . . . . . . . . . .5mW * Pb-Free Available (RoHS Compliant)
Applications
* HDTV/DTV Analog Inputs * Video Projectors * Computer Monitors * Set-top Boxes * Security Video
Pinout
ISL59440 (16 LD QSOP) TOP VIEW
NIC IN0 NIC IN1 GND IN2 NIC IN3 1 2 3 4 5 6 7 8 + 16 ENABLE 15 HIZ
* Broadcast Video Equipment
Ordering Information
PART NUMBER PART MARKING 59440 IA 59440 IAZ PACKAGE 16 Ld QSOP 16 Ld QSOP (Pb-free) PKG. DWG. # MDP0040 MDP0040
14
IN-
ISL59440IA*
13 OUT 12 V+ 11 V-
ISL59440IAZ* (Note)
*Add "-T7" or "-T13" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
10 S1 9 S0
Functional Diagram
EN0 S0 EN1 S1 DECODE IN0 IN1 EN2 EN3 IN2 IN3 - OUT + IN-
AMPLIFIER BIAS HIZ ENABLE ENABLE pin must be low in order to activate the HIZ state
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2005, 2007. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL59440
Absolute Maximum Ratings (TA = 25C)
Supply Voltage (V+ to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/s IN- Input Current (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Digital & Analog Input Current (Note 1) . . . . . . . . . . . . . . . . . . 50mA Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V
Thermal Information
Storage Temperature Range . . . . . . . . . . . . . . . . . . -65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . . -40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . . -40C to +125C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Curves JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Curves Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values. 2. Parts are 100% tested at +25C. Over temperature limits established by characterization and are not production tested.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER GENERAL IS Enabled IS Disabled Supply Current
V+ = +5V, V- = -5V, GND = 0V, TA = +25C, RL = 500 to GND unless otherwise specified. CONDITIONS MIN (Note 2) TYP MAX (Note 2) UNIT
DESCRIPTION
No load, VIN = 0V, ENABLE Low No load, VIN = 0V, ENABLE High No load, VIN = 0V, ENABLE High VIN = 2V, RL = 500, AV = 2 RL = 10 to GND
12.5 0.5
14.5 1 3
16.5 1.5 10
mA mA A V mA
Disabled Supply Current I+ Disabled Supply Current I-
VOUT IOUT VOS Ib+ IbROUT
Positive and Negative Output Swing Output Current Output Offset Voltage Input Bias Current Feedback Bias Current Output Resistance
3.5 80 -12
3.9 130 4 2.5 7 1.4 0.2 10 0.9 +12 -1.5 15
mV A A M M pF
VIN = 0V
-4 -15
HIZ = logic high, (DC), AV =1 HIZ = logic low, (DC), AV =1
RIN CIN ACL or AV ITRI LOGIC VH VL IIH IIL AC GENERAL - 3dB BW
Input Resistance Input Capacitance Voltage Gain Output Current in Three-state
VIN = 3.5V VIN = 224mVRMS, AV = 1 RF = RG = 500, VOUT = 3V VOUT = 0V 1.990 -20
2.005 6
2.020 20
V/V A
Input High Voltage (Logic Inputs) Input Low Voltage (Logic Inputs) Input High Current (Logic Inputs) Input Low Current (Logic Inputs)
2 0.8 55 -10 90 0 135 10
V V A A
-3dB Bandwidth
AV = 1, RF = 332, VOUT = 200mVP-P, CL = 1.6pF, CG = 0.6pF AV = 2, RF = RG = 511, VOUT = 2VP-P, CL = 5.5pF, CG = 0.6pF
400 200
MHz MHz
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FN6162.2 October 10, 2007
ISL59440
Electrical Specifications
PARAMETER 0.1dB BW V+ = +5V, V- = -5V, GND = 0V, TA = +25C, RL = 500 to GND unless otherwise specified. (Continued) CONDITIONS AV = 1, RF = 332, VOUT = 200mVP-P, CL = 1.6pF, CG = 0.6pF AV = 2, RF = RG = 511, VOUT = 2VP-P, CL = 5.5pF, CG = 0.6pF dG Differential Gain Error NTC-7, RL = 150, CL = 1.6pF, AV = 1 NTC-7, RL = 150, CL = 5.5pF, AV = 2 dP Differential Phase Error NTC-7, RL = 150, CL = 1.6pF, AV = 1 NTC-7, RL = 150, CL = 5.5pF, AV = 2 +SR Slew Rate 25% to 75%, AV = 1, VOUT = 4V, RL = 500, CL = 1.6pF 25% to 75%, AV = 2, VOUT = 5V, RL = 500, CL = 5.5pF -SR Slew Rate 25% to 75%, AV = 1, VOUT = 4V, RL = 500, CL = 1.6pF 25% to 75%, AV = 2, VOUT = 5V, RL = 500, CL= 5.5pF PSRR ISO Power Supply Rejection Ratio Channel Isolation DC, PSRR V+ and V- combined f = 10MHz, Ch-Ch crosstalk and off-isolation, CL = 5.5pF -50 MIN (Note 2) TYP 22 62 0.01 0.05 0.02 0.02 1053 1470 925 1309 -58 75 MAX (Note 2) UNIT MHz MHz % % V/s V/s V/s V/s dB dB
DESCRIPTION 0.1dB Bandwidth
SWITCHING CHARACTERISTICS VGLITCH Channel-to-Channel Switching Glitch ENABLE Switching Glitch HIZ Switching Glitch tSW-L-H tSW-H-L Channel Switching Time Low to High Channel Switching Time High to Low VIN = 0V, CL = 5.5pF, AV = 2 VIN = 0V, CL = 5.5pF, AV = 2 VIN = 0V, CL= 5.5pF, AV = 2 1.2V logic threshold to 10% movement of analog output 1.2V logic threshold to 10% movement of analog output 1 800 375 25 20 mVP-P mVP-P mVP-P ns ns
TRANSIENT RESPONSE tR, tF Rise and Fall Time, 10% to 90% AV = 1, RF = 332, VOUT = 100mVP-P, CL = 1.6pF, CG = 0.6pF AV = 2, RF = RG = 511, VOUT = 2VP-P, CL = 5.5pF, CG = 0.6pF tS OS 0.1% Settling Time Overshoot AV = 2, RF = RG = 511, VOUT = 2VP-P, CL = 5.5pF, CG = 0.6pF AV = 1, RF = 332, VOUT = 100mVP-P, CL = 1.6pF, CG = 0.6pF AV = 2, RF = RG = 511, VOUT = 2VP-P, CL = 5.5pF, CG = 0.6pF tPLH Propagation Delay - Low to High, 10% to 10% AV = 1, RF = 332, VOUT = 100mVP-P, CL = 1.6pF, CG = 0.6pF AV = 2, RF = RG = 511, VOUT = 2VP-P, CL = 5.5pF, CG = 0.6pF tPHL Propagation Delay- High to Low, 10% to 10% AV = 1, RF = 332, VOUT = 100mVP-P, CL = 1.6pF, CG = 0.6pF AV = 2, RF = RG = 511, VOUT = 2VP-P, CL = 5.5pF, CG = 0.6pF 0.65 1.51 9.0 17.85 12.65 0.54 0.99 0.57 1.02 ns ns ns % % ns ns ns ns
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FN6162.2 October 10, 2007
ISL59440 Typical Performance Curves VS = 5V, RL = 500 to GND, TA = 25C, unless otherwise specified.
5 4 3 NORMALIZED GAIN (dB) 2 1 0 -1 -2 -3 -4 -5 1M 10M 100M 1G FREQUENCY (Hz) CL INCLUDES 1.6pF BOARD CAPACITANCE CL = 1.6pF AV = 1 VOUT = 200mVP-P RF = 332 CL = 9.7pF CL = 7.2pF NORMALIZED GAIN (dB) CL = 5.5pF 5 4 3 2 1 0 -1 -2 -3 -4 -5 1M 10M 100M 1G RL = 150 RL = 75 AV = 1 VOUT = 200mVP-P CL= 1.6pF RF = 332
RL = 500 RL = 1k
FREQUENCY (Hz)
FIGURE 1. SMALL SIGNAL GAIN vs FREQUENCY vs CL
FIGURE 2. SMALL SIGNAL GAIN vs FREQUENCY vs RL
5 4 3 NORMALIZED GAIN (dB) 2 1 0 -1 -2 -3 -4 -5
AV = 2 VOUT = 2VP-P RG = RF = 511 NORMALIZED GAIN (dB)
5 4 3 2 1 0 -1 -2 -3 -4 -5 1G 1M 10M RL = 150 RL = 75 100M RL = 1k RL = 500 AV = 2 VOUT = 2VP-P CL = 5.5pF RG = RF = 511 RL = 75
CL = 9.7pF CL = 7.2pF CL = 5.5pF CL INCLUDES 1.6pF BOARD CAPACITANCE 1M 10M CL = 1.6pF
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 3. LARGE SIGNAL GAIN vs FREQUENCY vs CL
FIGURE 4. LARGE SIGNAL GAIN vs FREQUENCY vs RL
0.8 A =1 0.7 V V OUT = 200mVP-P RF = 332 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 1M 10M CL INCLUDES 1.6pF BOARD CAPACITANCE 100M 1G CL = 9.7pF CL = 7.2pF CL = 5.5pF NORMALIZED GAIN (dB) CL = 1.6pF
0.8 AV = 1 RL = 75 VOUT = 200mVP-P 0.6 CL = 1.6pF RL = 150 0.5 RF = 332 0.7 0.4 0.3 0.2 0.1 0 -0.1 -0.2 1M 10M 100M 1G RL = 1k
NORMALIZED GAIN (dB)
RL = 500
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. SMALL SIGNAL 0.1dB GAIN vs FREQUENCY vs CL
FIGURE 6. SMALL SIGNAL 0.1dB GAIN vs FREQUENCY vs RL
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FN6162.2 October 10, 2007
ISL59440 Typical Performance Curves VS = 5V, RL = 500 to GND, TA = 25C, unless otherwise specified.
0.2 0.1 0 NORMALIZED GAIN (dB) -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 1M 10M AV = 2 VOUT = 2VP-P RG = RF = 511 CL INCLUDES 1.6pF BOARD CAPACITANCE 100M 1G CL = 5.5pF CL = 1.6pF CL = 7.2pF NORMALIZED GAIN (dB) CL = 9.7pF 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 1M 10M RL = 1k 100M 1G RL = 500 AV = 2 VOUT = 2VP-P CL = 5.5pF RG = RF = 511 RL = 75
(Continued)
RL = 150
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 7. LARGE SIGNAL 0.1dB GAIN vs FREQUENCY vs CL
FIGURE 8. LARGE SIGNAL 0.1dB GAIN vs FREQUENCY vs RL
20 AV = 2 10 V = 200mV IN P-P 0 CL = 5.5pF RG = RF = 511 -10 PSRR (dB) -20 -30 -40 -50 -60 -70 -80 0.3M 1M 10M FREQUENCY (Hz) PSRR (V-) 100M 1G PSRR (V+) (dB)
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 0.001M 0.01M 0.1M 1M 3M 6M10M 100M 500M OFF ISOLATION CROSSTALK AV = 2 VIN = 1VP-P CL = 5.5pF RG = RF = 511
FREQUENCY (Hz)
FIGURE 9. PSRR CHANNELS
FIGURE 10. CROSSTALK AND OFF ISOLATION
24 -IIN CURRENT NOISE (pA/Hz)
AV = 1, RF = 500 INPUT VOLTAGE NOISE (nV/Hz)
60
AV = 1, RF = 500
20
50
16
40
12
30
8
20
4
10
0 0.1k 1k 10k FREQUENCY (Hz) 100k
0 0.1k 1k 10k 100k FREQUENCY (Hz)
FIGURE 11. INPUT NOISE vs FREQUENCY
FIGURE 12. INPUT NOISE vs FREQUENCY
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FN6162.2 October 10, 2007
ISL59440 Typical Performance Curves VS = 5V, RL = 500 to GND, TA = 25C, unless otherwise specified.
S0, S1 1V/DIV 1V/DIV S0, S1
(Continued)
0 10mV/DIV 0 1V/DIV VOUT
0 VOUT 0
20ns/DIV
20ns/DIV
FIGURE 13. CHANNEL TO CHANNEL SWITCHING GLITCH VIN = 0V, AV = 2
FIGURE 14. CHANNEL TO CHANNEL TRANSIENT RESPONSE VIN = 1V, AV = 2
ENABLE 1V/DIV 1V/DIV
ENABLE
0 20mV/DIV VOUT 0 2V/DIV
0
0
VOUT
20ns/DIV
20ns/DIV
FIGURE 15. ENABLE SWITCHING GLITCH VIN = 0V, AV = 2
FIGURE 16. ENABLE TRANSIENT RESPONSE VIN = 1V, AV = 2
HIZ 1V/DIV 1V/DIV
HIZ
0 200mV/DIV
0
0 VOUT
1V/DIV
VOUT 0
20ns/DIV
20ns/DIV
FIGURE 17. HIZ SWITCHING GLITCH VIN = 0V, AV = 2
FIGURE 18. HIZ TRANSIENT RESPONSE VIN = 1V, AV = 2
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FN6162.2 October 10, 2007
ISL59440 Typical Performance Curves VS = 5V, RL = 500 to GND, TA = 25C, unless otherwise specified.
160 120 OUTPUT VOLTAGE (mV) 80 40 0 -40 -80 -120 -160 TIME (4ns/DIV) AV = 1 CL = 1.6pF RF = 332 RL = 500 2.4 2.0 OUTPUT VOLTAGE (V) 1.6 1.2 0.8 0.4 0 -0.4 -0.8 AV = 2 CL= 5.5pF RG = RF = 511 RL = 500 TIME (4ns/DIV)
(Continued)
FIGURE 19. SMALL SIGNAL TRANSIENT RESPONSE
FIGURE 20. LARGE SIGNAL TRANSIENT RESPONSE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.4 POWER DISSIPATION (W) POWER DISSIPATION (W) 1.2 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) 893mW
QS OP JA 16 =1 12 C /W
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.2 1.0 0.8 633mW 0.6
J QS O
A =1
P1
0.4 0.2 0 0 25
58
6
C
/W
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
100 AV = 1, VOUT = 100mVP-P AV = 2, VOUT = 2VP-P OUTPUT RESISTANCE ()
10
AV = 2 1
AV = 1
0.1 0.1M
1M
10M FREQUENCY (Hz)
100M
1G
FIGURE 23. ROUT vs FREQUENCY
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FN6162.2 October 10, 2007
ISL59440 Pin Descriptions
PIN NUMBER 1, 3, 7 2 4 5 6 8 9 10 11 12 13 14 15 16 PIN NAME NIC IN0 IN1 GND IN2 IN3 S0 S1 VV+ OUT INHIZ ENABLE Circuit 1 Circuit 1 Circuit 4 Circuit 1 Circuit 1 Circuit 2 Circuit 2 Circuit 4 Circuit 4 Circuit 3 Circuit 1 Circuit 2 Circuit 2 EQUIVALENT CIRCUIT DESCRIPTION Not Internally Connected; it is recommended this pin be tied to ground to minimize crosstalk. Input for Channel 0 Input for Channel 1 Ground pin Input for Channel 2 Input for Channel 3 Channel selection pin LSB (binary logic code) Channel selection pin MSB (binary logic code) Negative power supply Positive power supply Output Inverting input of output amplifier Output disable (active high); there are internal pull-down resistors, so the device will be active with no connection; "HI" puts the output in high impedance state. Device enable (active low); there are internal pull-down resistors, so the device will be active with no connection; "HI" puts device into power-down mode.
V+ IN VCIRCUIT 1. LOGIC PIN 21k 33k + 1.2V V+ GND. VCIRCUIT 2.
V+ OUT V-
V+ GND VCAPACITIVELY COUPLED ESD CLAMP
CIRCUIT 3.
CIRCUIT 4.
AC Test Circuits
ISL59440 RG RF AV = 1, 2 VIN 50 OR 75 CL RS 475 OR 462.5 50 OR 75 TEST EQUIPMENT 50 OR 75 RG ISL59440 RF AV = 1, 2 RS CL 50 OR 75 TEST EQUIPMENT 50 OR 75
VIN 50 OR 75
FIGURE 24A. TEST CIRCUIT FOR MEASURING WITH A 50 OR 75 INPUT TERMINATED EQUIPMENT
FIGURE 24B. BACKLOADED TEST CIRCUIT FOR VIDEO CABLE APPLICATION. BANDWIDTH AND LINEARITY FOR RL LESS THAN 500 WILL BE DEGRADED.
NOTE: Figure 24A illustrates the optimum output load when connecting to input terminated equipment. Figure 24B illustrates backloaded test circuit for video cable applications.
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FN6162.2 October 10, 2007
ISL59440 Application Circuits
CF 332 *CL = CT + COUT VIN 50 0.6pF + Cg
PC BOARD CAPACITANCE
VOUT CT 1.6pF COUT 0pF RL = 500
0.4pF < CG < 0.7pF
*CL: TOTAL LOAD CAPACITANCE CT: TRACE CAPACITANCE COUT: OUTPUT CAPACITANCE
FIGURE 25A. GAIN OF 1 APPLICATION CIRCUIT
511 511 VIN 50 0.6pF + CG
PC BOARD CAPACITANCE
*CL = CT + COUT VOUT CT 1.6pF COUT 3.9pF RL = 500
0.4pF < CG < 0.7pF
FIGURE 25B. GAIN OF 2 APPLICATION CIRCUIT
Application Information
General
The ISL59440 is a 4:1 mux that is ideal as a matrix element in high performance switchers and routers. The ISL59440 is optimized to drive 5pF in parallel with a 500 load. The capacitance can be split between the PCB capacitance and an external load capacitance. Its low input capacitance and high input resistance provides excellent 50 or 75 terminations.
traces should not run parallel to each other. Small size surface mount resistors (604 or smaller) are recommended. CAPACITANCE AT THE OUTPUT The output amplifier is optimized for capacitance to ground (CL) directly on the output pin. Increased capacitance causes higher peaking with an increase in bandwidth. The optimum range for most applications is ~1.0pF to ~6pF. The optimum value can be achieved through a combination of PC board trace capacitance (CT) and an external capacitor (COUT). A good method to maintain control over the output pin capacitance is to minimize the trace length (CT) to the next component, and include a discrete surface mount capacitor (COUT) directly at the output pin. FEEDBACK RESISTOR VALUES The AC performance of the output amplifier is optimized with the feedback resistor network (RF, RG) values recommended in the application circuits. The amplifier bandwidth and gain peaking are directly effected by the value(s) of the feedback resistor(s) in unity gain and gain >1 configurations. Transient response performance can be tailored simply by changing these resistor values. Generally, lower values of RF and RG increase bandwidth and gain peaking. This has the effect of decreasing rise/fall times and increasing overshoot.
Parasitic Effects on Frequency Performance
CAPACITANCE AT THE INVERTING INPUT The AC performance of current-feedback amplifiers in the non-inverting gain configuration is strongly effected by stray capacitance at the inverting input. Stray capacitance from the inverting input pin to the output (CF), and to ground (CG), increase gain peaking and bandwidth. Large values of either capacitance can cause oscillation. The ISL59440 has been optimized for a 0.4pF to 0.7pF capacitance (CG). Capacitance (CF) to the output should be minimized. To achieve optimum performance the feedback network resistor(s) must be placed as close to the device as possible. Trace lengths greater than 1/4 inch combined with resistor pad capacitance can result in inverting input to ground capacitance approaching 1pF. Inverting input and output 9
FN6162.2 October 10, 2007
ISL59440
GROUND CONNECTIONS For the best isolation and crosstalk rejection, the GND pin and NIC pins must connect to the GND plane. CONTROL SIGNALS S0, S1, ENABLE, HIZ - These pins are TTL/CMOS compatible control inputs. The S0 pin selects which one of the inputs connect to the output. The ENABLE, HIZ pins are used to disable the part to save power and three-state the output amplifiers, respectively. For control signal rise and fall times less than 10ns the use of termination resistors close to the part will minimize transients coupled to the output. POWER-UP CONSIDERATIONS The ESD protection circuits use internal diodes from all pins the V+ and V- supplies. In addition, a dV/dT- triggered clamp is connected between the V+ and V- pins, as shown in the Equivalent Circuits 1 through 4 section of the "Pin Descriptions" on page 8. The dV/dT triggered clamp imposes a maximum supply turn-on slew rate of 1V/s. Damaging currents can flow for power supply rates-of-rise in excess of 1V/s, such as during hot plugging. Under these conditions, additional methods should be employed to ensure the rate of rise is not exceeded. Consideration must be given to the order in which power is applied to the V+ and V- pins, as well as analog and logic input pins. Schottky diodes (Motorola MBR0550T or equivalent) connected from V+ to ground and V- to ground (Figure 26) will shunt damaging currents away from the internal V+ and V- ESD diodes in the event that the V+ supply is applied to the device before the V- supply. If positive voltages are applied to the logic or analog video input pins before V+ is applied, current will flow through the internal ESD diodes to the V+ pin. The presence of large decoupling capacitors and the loading effect of other circuits connected to V+, can result in damaging currents through the ESD diodes and other active circuits within the device. Therefore, adequate current limiting on the digital and analog inputs is needed to prevent damage during the time the voltages on these inputs are more positive than V+. ENABLE AND POWER DOWN STATES The enable pin is active low. An internal pull-down resistor ensures the device will be active with no connection to the ENABLE pin. The Power Down state is established when a logic high (>2V) is placed on the ENABLE pin. In the Power Down state, the output has no leakage but has a large capacitance (on the order of 15pF), and is capable of being back-driven. Under this condition, large incoming slew rates can cause fault currents of tens of mA. Do not use this state as a high Z state for applications driving more than one mux on a common output. LIMITING THE OUTPUT CURRENT No output short circuit current limit exists on this part. All applications need to limit the output current to less than 50mA. Adequate thermal heat sinking of the parts is also required. HIZ STATE An internal pull-down resistor connected to the HIZ pin ensures the device will be active with no connection to the HIZ pin. The HIZ state is established within approximately 30ns (Figure 18) by placing a logic high (> 2V) on the HIZ pin. If the HIZ state is selected, the output is a high impedance 1.4M. Use this state to control the logic when more than one mux shares a common output. In the HIZ state the output is three-stated, and maintains its high Z even in the presence of high slew rates. The supply current during this state is basically the same as the active state.
V+ SUPPLY SCHOTTKY PROTECTION LOGIC POWER GND SIGNAL DE-COUPLING CAPS V- SUPPLY S0 GND IN0 IN1 VVVV+ VVV+ V+ OUT V+ V+ LOGIC CONTROL EXTERNAL CIRCUITS
FIGURE 26. SCHOTTKY PROTECTION CIRCUIT
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FN6162.2 October 10, 2007
ISL59440 PC Board Layout
The frequency response of this circuit depends greatly on the care taken in designing the PC board. The following are recommendations to achieve optimum high frequency performance from your PC board. * The use of low inductance components such as chip resistors and chip capacitors is strongly recommended. * Match channel-channel analog I/O trace lengths and layout symmetry. This will minimize propagation delay mismatches. * Maximize use of AC de-coupled PCB layers. All signal I/O lines should be routed over continuous ground planes (i.e. no split planes or PCB gaps under these lines). Avoid vias in the signal I/O lines. * Use proper value and location of termination resistors. Termination resistors should be as close to the device as possible. * When testing use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. * Minimum of 2 power supply de-coupling capacitors are recommended (1000pF, 0.01F) as close to the device as possible - Avoid vias between the cap and the device because vias add unwanted inductance. Larger caps can be farther away. When vias are required in a layout, they should be routed as far away from the device as possible. * The NIC pins are placed on both sides of the input pins. These pins are not internally connected to the die. It is recommended these pins be tied to ground to minimize crosstalk.
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FN6162.2 October 10, 2007
ISL59440 Quarter Size Outline Plastic Packages Family (QSOP)
A D N (N/2)+1
MDP0040
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY INCHES SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES
PIN #1 I.D. MARK
A A1 A2 b
0.068 0.006 0.056 0.010 0.008 0.193 0.236 0.154 0.025 0.025 0.041 16
0.068 0.006 0.056 0.010 0.008 0.341 0.236 0.154 0.025 0.025 0.041 24
0.068 0.006 0.056 0.010 0.008 0.390 0.236 0.154 0.025 0.025 0.041 28
Max. 0.002 0.004 0.002 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference
1, 3 2, 3 Rev. F 2/07
E
E1
1 B 0.010 CAB
(N/2)
c D E
e C SEATING PLANE 0.004 C 0.007 CAB b
H
E1 e L L1 N
L1 A c SEE DETAIL "X"
NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.010 A2 GAUGE PLANE L 44 DETAIL X
A1
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN6162.2 October 10, 2007

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